`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:30:52 09/14/2012
// Design Name:   controlador_leds
// Module Name:   C:/Users/maye/Desktop/taller/lab2/lab3/contr_led_pru.v
// Project Name:  lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: controlador_leds
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module contr_led_pru;

	// Inputs
	reg clk_i;
	reg [1:0] leds_i;

	// Outputs
	wire [1:0] leds_o;

	// Instantiate the Unit Under Test (UUT)
	controlador_leds uut (
		.clk_i(clk_i), 
		.leds_i(leds_i), 
		.leds_o(leds_o)
	);

	always begin 
		#50 clk_i=~clk_i;
	end
	initial begin
		// Initialize Inputs
		clk_i = 0;
		leds_i = 1;

		// Wait 100 ns for global reset to finish
		#300;
		leds_i = 0;
        
		// Add stimulus here

	end
      
endmodule

